The invention relates to a testing method of a chip, and more particularly, to a testing method of a chip for preventing sampling errors due to asynchronous effect.
Chip testing is done during manufacture process to confirm the manufacturing quality. When testing, ideal output of chips under specific input is simulated by a computer and then recorded. The specific input is then applied to the chips and the real output and the ideal output of the chips are compared to identify if there have manufacturing defects of the chip.
Different operation frequencies are required for various electronic devices. For example, a chip is capable of two different operating frequencies. However because the asynchronous effect, it is difficult to test a chip capable of two different operating frequencies.
Asynchronous effect is described with reference to FIGS. 1 and 2. FIG. 1 shows a flip-flop circuit which might be included in a chip.
As shown in FIG. 1, an input signal D2 is sampled by a flip-flop 2 according to the clock signal CLK2, and then generating an output signal Q2. Another input signal D1 is sampled by a flip-flop 1 according to the clock signal CLK1, and then generating an output signal Q1. Wherein the input signal D1 of the flip-flop 1 is the output signal Q2 of the flip-flop 2 after passing through a logic circuit Lg. However, latency between the signals Q2 and D1 is dependent on the logic circuit Lg, which may be 1.7˜2.3 nano-seconds (ns).
FIG. 2 shows a wave diagram of the clock signals CLK1 and CLK2 of FIG. 1. The operating frequency of CLK1 is higher than CLK2; and the operating frequency of CLK1 is not integral times to CLK2. For example, the operating frequency of CLK1 may be 250 MHz and the operating frequency of CLK2 may be 66 MHz.
The output signal Q2 is input to the logic circuit Lg after sampling the input signal D2 at 30 ns by the flip-flop 2. If the latency of the logic circuit Lg is 1.7 ns˜2.3 ns, the input signal D1 is output from the logic circuit at 31.7 ns˜32.3 ns. As a result, according to the CLK1, the flip-flop 1 would sample the input signal D1 at 32 ns or at 36 ns. Obviously, there has two different sampling timing in one clock signal CLK1 which will cause the sampling error in flip-flop 1, and that is called the asynchronous effect.
Similarly, as shown in FIG. 2, the asynchronous effect exists no matter the input signal D2 is sampled at 15 ns and the latency of the logic circuit Lg is 0.8 ns˜1.2 ns, or the input signal D2 is sampled at 45 ns and the latency of the logic circuit Lg is 2.8ns ˜3.2 ns.
In order to prevent asynchronous effect, latency of the logic circuit Lg cannot exceed 1 ns(0.8 ns˜1.2 ns), 2 ns(1.7 ns˜2.3 ns) or 3 ns(2.8 ns˜3.2 ns). It is difficult to design a chip with the limitation of logic circuit latency.